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| author | Thierry Reding <[email protected]> | 2020-06-11 19:59:25 +0200 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2020-06-25 09:29:46 +0200 |
| commit | eb6563a681e2fdf5e33a3ede03c8768059d3a8d3 (patch) | |
| tree | eded64bcf46a6ca84c918efecb57204e9e12a4a2 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 7fb099528bbe92157a5e2bdc94b6f5e0269f0dd6 (diff) | |
ARM: tegra: Add parent clock to DSI output
The DSI output needs to specify a parent clock that will be used to
drive both the output and the display controller.
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions