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| author | Madhav Chauhan <[email protected]> | 2018-10-15 17:28:03 +0300 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2018-10-22 15:14:40 +0300 |
| commit | d1aeb5f399d98443fd1f4b26480519379cb9cec8 (patch) | |
| tree | 7ee067747b317fa42573b8718df7a813c78678b5 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 7b56caf36376f6d714a56ae42865da0a5ef7b2fc (diff) | |
drm/i915/icl: Configure DSI transcoder timings
As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.
v2: Remove TRANS_TIMING_SHIFT usage
v3 by Jani:
- Rebase
- Reduce temp variable use
- Checkpatch fix
Signed-off-by: Madhav Chauhan <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/525949ae4e919a4f2b807d606234322534656048.1539613303.git.jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions