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| author | Shubhrajyoti Datta <[email protected]> | 2022-02-22 18:39:03 +0530 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2022-03-29 10:17:49 -0700 |
| commit | a6aa462c3efc144808b0cf8a0fe993d4fe2c079a (patch) | |
| tree | 9e4ac23aa71109930d0a79d3475f72064b0bea65 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | d583804c97c5ae7a7eba9c44982adcb106c2d160 (diff) | |
clk: zynq: Update the parameters to zynq_clk_register_periph_clk
In case there are only one gate or the two_gate is 0 the clk1 clock
passed is not used. We are passing 0 which is arm_pll.
Pass a invalid clock instead.
Signed-off-by: Shubhrajyoti Datta <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions