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| author | Abhinav Kumar <[email protected]> | 2018-06-07 13:50:29 -0700 |
|---|---|---|
| committer | Sean Paul <[email protected]> | 2018-07-26 10:40:15 -0400 |
| commit | 2d0b10fc5111bb4a902e9be378496d04c401ab81 (patch) | |
| tree | 252ad33176f951e4297d60e8107ffc79e093ef96 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | bb676df12b5e81cab57d1a212a6e9cfc343875a7 (diff) | |
drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor
Make the pclk_rate u64 to accommodate higher pixel clock
rates.
Changes in v3:
- Converted pclk_rate to u32 (Archit)
- Rebase on dsi cleanup set in msm-next
Cc: Sibi Sankar <[email protected]>
Cc: Archit Taneja <[email protected]>
Signed-off-by: Abhinav Kumar <[email protected]>
Signed-off-by: Sean Paul <[email protected]>
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions