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| author | Mateusz Kwiatkowski <[email protected]> | 2022-12-07 12:53:24 +0100 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2023-01-09 15:21:31 +0100 |
| commit | 273c417658c83026741ded0c34cec9caab41e97f (patch) | |
| tree | bc8f868f71ab36784e4b7f3454178c1e89d7c361 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 6c37c9c65d2c792ddee3e33e595a498592bf9735 (diff) | |
drm/vc4: crtc: Fix timings for VEC modes
This commit fixes vertical timings of the VEC (composite output) modes
to accurately represent the 525-line ("NTSC") and 625-line ("PAL") ITU-R
standards.
Previous timings were actually defined as 502 and 601 lines, resulting
in non-standard 62.69 Hz and 52 Hz signals being generated,
respectively.
Changes to vc4_crtc.c have also been made, to make the PixelValve
vertical timings accurately correspond to the DRM modeline in interlaced
modes. The resulting VERTA/VERTB register values have been verified
against the reference values set by the Raspberry Pi firmware.
Signed-off-by: Mateusz Kwiatkowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Maxime Ripard <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions