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| author | Thierry Reding <[email protected]> | 2014-11-07 16:10:41 +0100 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2015-05-04 12:54:23 +0200 |
| commit | 242b1d713386e8e2fd7f62cc1ed4681a12290848 (patch) | |
| tree | e91adedcd99c0700c64e53bc4fa72117e7ade8ef /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | d1313e7896e932a92e21912850ef034e58571b66 (diff) | |
memory: tegra: Add Tegra132 support
The memory controller on Tegra132 is very similar to the one found on
Tegra124. But the Denver CPUs don't have an outer cache, so dcache
maintenance is done slightly differently.
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions