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| author | Mathieu Desnoyers <[email protected]> | 2022-11-22 15:39:19 -0500 |
|---|---|---|
| committer | Peter Zijlstra <[email protected]> | 2022-12-27 12:52:14 +0100 |
| commit | 171586a6ab66fb6be064e399ac2024ab459dfcf9 (patch) | |
| tree | c76bb9b35b58ad3a200eb878a0c10b472ced2a5e /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | a94af3c58462d23c45879e1bbe86ed5702d5bd86 (diff) | |
selftests/rseq: riscv: Template memory ordering and percpu access mode
Introduce a rseq-riscv-bits.h template header which is internally included
to generate the static inline functions covering:
- relaxed and release memory ordering,
- per-cpu-id and per-mm-cid per-cpu data access.
Signed-off-by: Mathieu Desnoyers <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
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