diff options
| author | Shawn Guo <[email protected]> | 2016-07-08 17:00:39 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2016-08-31 15:24:23 +0200 |
| commit | 0e125a5facf857567f8bb6dbb1ceefac14b2fa64 (patch) | |
| tree | cbcbae8813c7018412c576978248113360f93148 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 694d0d0bb2030d2e36df73e2d23d5770511dbc8d (diff) | |
tty: amba-pl011: define flag register bits for ZTE device
For some reason we do not really understand, ZTE hardware designers
choose to define PL011 Flag Register bit positions differently from
standard ones as below.
Bit Standard ZTE
-----------------------------------
CTS 0 1
DSR 1 3
BUSY 3 8
RI 8 0
Let's define these bits into vendor data and get ZTE PL011 supported
properly.
Signed-off-by: Shawn Guo <[email protected]>
Acked-by: Russell King <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions