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| author | Ville Syrjälä <[email protected]> | 2023-02-14 00:52:55 +0200 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2023-02-17 23:40:56 +0200 |
| commit | 050db7d70c3c6cf72d11dde8961f953f990b9c6e (patch) | |
| tree | 73e4ecb14311f2dfff38a9fc83213f30b4d99f57 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 9c0cd4bb9a2da8c69cd9331ba1824bca027d6090 (diff) | |
drm/i915: Define transcoder timing register bitmasks
Define the contents of the transcoder timing registers using
REG_GENMASK() & co. For ease of maintenance let's just define
the bitmasks with the full 16bit width (also used by the
current hand rolled stuff) even though not all bits are actually
used. None of the unsued bits have ever contained anything.
Jani spotted that the CRT load detection code did use narrower
bitmasks, so that is now going to change. But that is fine
since any garbage in the high bits would have been caught by
the state checker that always used the full 16bit masks.
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jani Nikula <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions