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| author | Kishon Vijay Abraham I <[email protected]> | 2021-03-10 17:38:36 +0530 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2021-03-30 23:33:18 +0530 |
| commit | 7e52a39f1942b771213678c56002ce90a2f126d2 (patch) | |
| tree | 97896eb0b6eb6584947df337c9bc2cf4f7957893 /tools/perf/scripts/python/bin/export-to-sqlite-report | |
| parent | 549cb1ae3e56e71ccd2547c3c40ff2556af8ce49 (diff) | |
phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module
present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in
wiz. However during cleanup, it removed only the MUX clock provider.
Remove the DIVIDER clock provider here.
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/export-to-sqlite-report')
0 files changed, 0 insertions, 0 deletions