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| author | AngeloGioacchino Del Regno <[email protected]> | 2022-04-27 15:23:27 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2022-05-05 22:59:10 +0200 |
| commit | 6f81fdded0d024c7d4084d434764f30bca1cd6b1 (patch) | |
| tree | ec96dbc9f3820e80f4a2cb8de8f1036f6489b4e6 /tools/perf/scripts/python/bin/export-to-sqlite-report | |
| parent | bb0b197aadd928f52ce6f01f0ee977f0a08cf1be (diff) | |
serial: 8250_mtk: Make sure to select the right FEATURE_SEL
Set the FEATURE_SEL at probe time to make sure that BIT(0) is enabled:
this guarantees that when the port is configured as AP UART, the
right register layout is interpreted by the UART IP.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Cc: stable <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/export-to-sqlite-report')
0 files changed, 0 insertions, 0 deletions