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| author | Martin Leung <[email protected]> | 2019-07-17 16:08:19 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-08-15 10:54:27 -0500 |
| commit | 5ec43eda85506ddc2f91c3a4e28b38da3f14cf1e (patch) | |
| tree | 62aa9ea986f025062d7ed0dd8b45708aca89af26 /tools/perf/scripts/python/bin/export-to-sqlite-report | |
| parent | 39bdac36cc139dfaf4ff324250319b79c6c224b8 (diff) | |
drm/amd/display: enabling seamless boot sequence for dcn2
[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes
[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.
This is part 2 of 2 for seamless boot NV10
Signed-off-by: Martin Leung <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/export-to-sqlite-report')
0 files changed, 0 insertions, 0 deletions