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| author | Dmitry Baryshkov <[email protected]> | 2024-08-04 08:40:06 +0300 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2024-08-15 17:10:13 -0500 |
| commit | 362be5cbaec2a663eb86b7105313368b4a71fc1e (patch) | |
| tree | 092d654ba934149afdafde3781692d51cf5df11e /tools/perf/scripts/python/bin/export-to-sqlite-report | |
| parent | 0e93c6320ecde0583de09f3fe801ce8822886fec (diff) | |
clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL
According to msm-5.10 the lucid 5lpe PLLs have require slightly
different configuration that trion / lucid PLLs, it doesn't set
PLL_UPDATE_BYPASS bit. Add corresponding function and use it for the
display clock controller on Qualcomm SM8350 platform.
Fixes: 205737fe3345 ("clk: qcom: add support for SM8350 DISPCC")
Signed-off-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/export-to-sqlite-report')
0 files changed, 0 insertions, 0 deletions