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authorKishon Vijay Abraham I <[email protected]>2021-03-10 17:38:38 +0530
committerVinod Koul <[email protected]>2021-03-30 23:33:22 +0530
commit040cbe7687316e265199ce892d3f7c24c041aaec (patch)
treee6cd857a7e9e484a69dcedfb7dc0706e1c03f664 /tools/perf/scripts/python/bin/export-to-sqlite-report
parent6ecac2f8ff1abbae464d6ce451ee07d49cdb2982 (diff)
phy: ti: j721e-wiz: Model the internal clocks without device tree input
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled the internal clocks depending on the subnodes that are populated in device tree. However recent discussions in the mailing list [1] suggested to just add #clock cells in the parent DT node and model the clocks within the driver. Model the mux clocks without device tree input for AM64x SoC. Don't remove the earlier design since DT nodes for J7200 and J721e are already upstreamed. [1] -> http://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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