drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll

There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list.  We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.

Cc: Douglas Anderson <[email protected]>
Signed-off-by: zain wang <[email protected]>
Signed-off-by: Sean Paul <[email protected]>
Signed-off-by: Thierry Escande <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]>
Signed-off-by: Enric Balletbo i Serra <[email protected]>
Tested-by: Marek Szyprowski <[email protected]>
Reviewed-by: Archit Taneja <[email protected]>
Signed-off-by: Andrzej Hajda <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

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