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authorRussell King <rmk+kernel@arm.linux.org.uk>2015-07-22 10:39:27 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-10-09 17:17:34 +0100
commit426701d0ccc13a2819fd99938ec50a888817e77d (patch)
tree51ac75c6c6e826cb3ee03de4a203bfe2a7c6f131 /tools/perf/scripts/python/bin/export-to-postgresql-report
parentd0c96d168021a60555c692d860334814cc694d8b (diff)
drm: bridge/dw_hdmi: adjust pixel clock values in N calculation
Adjust the pixel clock values in the N calculation to match the more accurate clock values we're given by the DRM subsystem, which are the kHz pixel rate, with any fractional kHz rounded down in the case of the non-240, non-480 line modes, or rounded up for the others. So, 25.20 / 1.001 => 25175 27.00 * 1.001 => 27027 74.25 / 1.001 => 74176 148.50 / 1.001 => 148352 DRM derives these rates from the EDID CEA mode identifiers, which are looked up in the tables in drivers/gpu/drm/drm_edid.c. The values on the right are the clock values found in these tables, and are currently expected to be passed to the HDMI driver unchanged. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'tools/perf/scripts/python/bin/export-to-postgresql-report')
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