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| author | Jack Zhang <[email protected]> | 2020-06-29 10:06:49 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-07-15 12:45:28 -0400 |
| commit | c8466cc0d2a419e7659bff5161440741cb96ab1e (patch) | |
| tree | 0ae6b6313369f73cd356f000a2d427a39bea7344 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | a3302729368d2e4c6c6a1918179c8c53bec79219 (diff) | |
drm/amd/sriov skip vcn powergating and dec_ring_test
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.
2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.
V2: delete unneccessary white lines and refine implementation.
Signed-off-by: Jack Zhang <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions