diff options
| author | Jie Wang <[email protected]> | 2021-11-10 21:42:50 +0800 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2021-11-10 14:20:43 +0000 |
| commit | beb27ca451a57a1c0e52b5268703f3c3173c1f8c (patch) | |
| tree | ca120b3d02a08fbe85fb7d00cfd656339c02b237 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | 3b4c6566c158e0449d490165c1a64d9e410b3007 (diff) | |
net: hns3: fix ROCE base interrupt vector initialization bug
Currently, NIC init ROCE interrupt vector with MSIX interrupt. But ROCE use
pci_irq_vector() to get interrupt vector, which adds the relative interrupt
vector again and gets wrong interrupt vector.
So fixes it by assign relative interrupt vector to ROCE instead of MSIX
interrupt vector and delete the unused struct member base_msi_vector
declaration of hclgevf_dev.
Fixes: 46a3df9f9718 ("net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support")
Signed-off-by: Jie Wang <[email protected]>
Signed-off-by: Guangbin Huang <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions