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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-07 15:10:00 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-18 08:58:06 +0200 |
| commit | ba5284ebe497044f37c9bb9c7b1564932f4b6610 (patch) | |
| tree | 1faaa860b92664bfaeebb6deb7bf0a98bc672c4b /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
clk: renesas: r8a779g0: Add SASYNCPER clocks
On R-Car V4H, all PLLs except PLL5 support Spread Spectrum and/or
Fractional Multiplication to reduce electromagnetic interference.
Add the SASYNCPER and SASYNCPERD[124] clocks, which are used as clock
sources for modules that must not be affected by Spread Spectrum and/or
Fractional Multiplication.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/d0f35c35e1f96c5a649ab477e7ba5d8025957cd0.1665147497.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions