diff options
author | Björn Töpel <[email protected]> | 2024-10-24 12:03:51 -0700 |
---|---|---|
committer | Namhyung Kim <[email protected]> | 2024-10-30 23:39:34 -0700 |
commit | 8c0d1202bad3aa6e40fb078dc08158f0bb4e03e2 (patch) | |
tree | fdeda0ab1775eb24c4ee6b8717cb93fd46b39344 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
parent | 54afc56db221c831479dd1b59eb0657c078355d1 (diff) |
perf, riscv: Wire up perf trace support for RISC-V
RISC-V does not currently support perf trace, since the system call
table is not generated.
Perform the copy/paste exercise, wiring up RISC-V system call table
generation.
Signed-off-by: Björn Töpel <[email protected]>
Tested-by: Alexandre Ghiti <[email protected]>
Cc: Anup Patel <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Albert Ou <[email protected]>
Cc: [email protected]
Cc: Atish Patra <[email protected]>
Cc: Paul Walmsley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Namhyung Kim <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions