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| author | David S. Miller <[email protected]> | 2022-09-17 20:13:41 +0100 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2022-09-17 20:13:41 +0100 |
| commit | 44a8535fb87c5503ce01121278ac3058eef701ec (patch) | |
| tree | 20f8b43d78dc13bdc85ac9b8e43a2838f741fdd5 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | 5947b7f794ca5b96fa097d8d73259aaf18878c31 (diff) | |
| parent | 85a5f9638313a1df7e84e9ea66ecd216133215c2 (diff) | |
Merge branch 'octeontx2-cn10k-ptp'
From: Naveen Mamindlapalli <[email protected]>
To: <[email protected]>, <[email protected]>, <[email protected]>,
<[email protected]>, <[email protected]>,
<[email protected]>, <[email protected]>,
<[email protected]>, <[email protected]>
Cc: Naveen Mamindlapalli <[email protected]>
Subject: [net-next PATCH 0/4] Add PTP support for CN10K silicon
Date: Sat, 10 Sep 2022 13:24:12 +0530 [thread overview]
Message-ID: <[email protected]> (raw)
This patchset adds PTP support for CN10K silicon, specifically
to workaround few hardware issues and to add 1-step mode.
Patchset overview:
Patch #1 returns correct ptp timestamp in nanoseconds captured
when external timestamp event occurs.
Patch #2 adds 1-step mode support.
Patch #3 implements software workaround to generate PPS output properly.
Patch #4 provides a software workaround for the rollover register default
value, which causes ptp to return the wrong timestamp.
====================
Acked-by: Richard Cochran <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions