aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/arm-cs-trace-disasm.py
diff options
context:
space:
mode:
authorManivannan Sadhasivam <[email protected]>2023-03-14 13:34:31 +0530
committerBjorn Andersson <[email protected]>2023-03-15 15:17:08 -0700
commit43aa006e074c4dcaf7493895fb2bd4af16d7c0ab (patch)
treec266fe68c4f50a57c8f07bfe0780b3455c0e06a5 /tools/perf/scripts/python/arm-cs-trace-disasm.py
parent94b1d58f887a147d9a0e8bccc7fffd067c5b9588 (diff)
dt-bindings: arm: msm: Fix register regions used for LLCC banks
Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions