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authorBiju Das <[email protected]>2022-04-02 09:13:24 +0100
committerGeert Uytterhoeven <[email protected]>2022-04-13 13:56:09 +0200
commit20e63d3948985672b9e8efa98ff3643d91378e84 (patch)
treea9d8f212f6d768637703345531c34db6c9b1de02 /tools/perf/scripts/python/arm-cs-trace-disasm.py
parent4e44055440e1fef93e830bd06111bbbb0a89fa44 (diff)
arm64: dts: renesas: r9a07g043: Add SDHI nodes
Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Lad Prabhakar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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