aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/Perf-Trace-Util
diff options
context:
space:
mode:
authorLu Baolu <[email protected]>2023-11-22 11:26:07 +0800
committerJoerg Roedel <[email protected]>2023-11-27 11:07:53 +0100
commite7ad6c2a4b1aa710db94060b716f53c812cef565 (patch)
tree994a36e11573419f3ae1c02eb4570bf7364e315f /tools/perf/scripts/python/Perf-Trace-Util
parent85b80fdffa867d75dfb9084a839e7949e29064e8 (diff)
iommu/vt-d: Fix incorrect cache invalidation for mm notification
Commit 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when invalidating TLBs") moved the secondary TLB invalidations into the TLB invalidation functions to ensure that all secondary TLB invalidations happen at the same time as the CPU invalidation and added a flush-all type of secondary TLB invalidation for the batched mode, where a range of [0, -1UL) is used to indicates that the range extends to the end of the address space. However, using an end address of -1UL caused an overflow in the Intel IOMMU driver, where the end address was rounded up to the next page. As a result, both the IOTLB and device ATC were not invalidated correctly. Add a flush all helper function and call it when the invalidation range is from 0 to -1UL, ensuring that the entire caches are invalidated correctly. Fixes: 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when invalidating TLBs") Cc: [email protected] Cc: Huang Ying <[email protected]> Cc: Alistair Popple <[email protected]> Tested-by: Luo Yuzhang <[email protected]> # QAT Tested-by: Tony Zhu <[email protected]> # DSA Reviewed-by: Jason Gunthorpe <[email protected]> Reviewed-by: Alistair Popple <[email protected]> Signed-off-by: Lu Baolu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util')
0 files changed, 0 insertions, 0 deletions