diff options
| author | Minghuan Lian <[email protected]> | 2012-09-24 13:50:52 +0800 |
|---|---|---|
| committer | Kumar Gala <[email protected]> | 2012-09-27 07:31:58 -0500 |
| commit | 59c58c324a81cfb08c490384a7c292b82609673a (patch) | |
| tree | c4dfb067e4ed4db88d1f5fac7d319ba7e0f70feb /tools/perf/scripts/python/Perf-Trace-Util | |
| parent | 7844663a31e97930e3949430573452ac245bfdd5 (diff) | |
powerpc/fsl-pci: use 'Header Type' to identify PCIE mode
The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, some latest silicons do not support this
functionality. According to PCIE specification, 'Header Type' offset 0x0e
is used to indicate header type, so change code to use 'Header Type' field
to judge PCIE mode. Because FSL PCI controller does not support
'Header Type', patch still uses 'Programming Interface' to identify PCI
mode.
Signed-off-by: Minghuan Lian <[email protected]>
Signed-off-by: Roy Zang <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util')
0 files changed, 0 insertions, 0 deletions