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author | Paul Burton <[email protected]> | 2014-07-14 10:32:13 +0100 |
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committer | Ralf Baechle <[email protected]> | 2014-08-02 00:06:45 +0200 |
commit | e19d5dbad5b4ea445be29d7146dd6a1cd9b51b97 (patch) | |
tree | 91feeefdbd1a7a1710e95b5e80dc296546102e7e /tools/perf/scripts/python/Perf-Trace-Util/lib | |
parent | 4af94d5d09bace4f351d7ce5f5e18da07777eb63 (diff) |
MIPS: define MAAR register accessors & bits
Add accessor macros for the Memory Accessibility Attribute Registers
(MAARs), the bits contained within the MAARs & the Config5.MRP bit
indicating their presence. The only current use of the MAARs is to
enable speculative accesses to regions of memory. Besides the potential
performance benefits of speculative accesses, they are a requirement
for the P5600 core to handle non-128b-aligned MSA vector loads & stores
rather than generating an address error.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/7329/
Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib')
0 files changed, 0 insertions, 0 deletions