diff options
| author | Catalin Marinas <[email protected]> | 2014-07-24 14:14:42 +0100 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2014-07-25 13:12:15 +0100 |
| commit | 72c5839515260dce966cd24f54436e6583288e6c (patch) | |
| tree | f6a65a5899490397eaa8c6a609452d365f05273d /tools/perf/scripts/python/Perf-Trace-Util/lib | |
| parent | ecb3c2bbf233d0c8d6e48009afa52c45c0204857 (diff) | |
arm64: gicv3: Allow GICv3 compilation with older binutils
GICv3 introduces new system registers accessible with the full msr/mrs
syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent
binutils understand the new syntax. This patch introduces msr_s/mrs_s
assembly macros which generate the equivalent instructions above and
converts the existing GICv3 code (both drivers/irqchip/ and
arch/arm64/kernel/).
Signed-off-by: Catalin Marinas <[email protected]>
Reported-by: Olof Johansson <[email protected]>
Tested-by: Olof Johansson <[email protected]>
Suggested-by: Mark Rutland <[email protected]>
Acked-by: Mark Rutland <[email protected]>
Acked-by: Jason Cooper <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Marc Zyngier <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib')
0 files changed, 0 insertions, 0 deletions