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authorIlpo Järvinen <[email protected]>2023-01-16 12:08:39 +0200
committerLee Jones <[email protected]>2023-01-27 10:36:29 +0000
commit6052a005caf9cd484fe6368a31c736ac17ebaf66 (patch)
tree0e52513de109f394ceab092678adefee5345f378 /tools/perf/scripts/python/Perf-Trace-Util/lib
parent603aed8ffd4c9cb633c05a514cfb5e8ca6b0751d (diff)
mfd: intel-m10-bmc: Support multiple CSR register layouts
There are different addresses for the MAX10 CSR registers. Introducing a new data structure m10bmc_csr_map for the register definition of MAX10 CSR. Provide the csr_map for SPI. Co-developed-by: Tianfei zhang <[email protected]> Signed-off-by: Tianfei zhang <[email protected]> Reviewed-by: Russ Weight <[email protected]> Reviewed-by: Xu Yilun <[email protected]> Signed-off-by: Ilpo Järvinen <[email protected]> Signed-off-by: Lee Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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