diff options
| author | Chao Fu <[email protected]> | 2014-02-12 15:29:05 +0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2014-02-16 09:15:23 +0800 |
| commit | 1acbdeb92c87fc18eade0815dedc257fe45b88b7 (patch) | |
| tree | 8e4b34fade904bbd4e01c94f90212d9ad6654eba /tools/perf/scripts/python/Perf-Trace-Util/lib | |
| parent | 38dbfb59d1175ef458d006556061adeaa8751b72 (diff) | |
spi/fsl-dspi: Convert to use regmap and add big-endian support
Freescale DSPI module will have two endianess in different platform,
but ARM is little endian. So when DSPI in big endian, core in little endian,
readl and writel can not adjust R/W register in this condition.
This patch will remove general readl/writel, and import regmap mechanism.
Data endian will be transfered in regmap APIs.
Documents: dspi add bool "big-endian" in dts node if DSPI module
work in big endian.
Signed-off-by: Chao Fu <[email protected]>
Reviewed-by: Xiubo Li <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib')
0 files changed, 0 insertions, 0 deletions