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authorTvrtko Ursulin <[email protected]>2023-02-16 09:21:23 +0000
committerTvrtko Ursulin <[email protected]>2023-02-17 10:31:58 +0000
commit1008266e31a0cb86cf8ac18eb77047283ae2b800 (patch)
tree95c4fd075129b84aa1eadf865d3177c865e74710 /tools/perf/scripts/python/Perf-Trace-Util/lib
parent01361096a33a81cc224e12e8cf06240f12737365 (diff)
drm/i915: Consolidate TLB invalidation flow
As the logic for selecting the register and corresponsing values grew, the code become a bit unsightly. Consolidate by storing the required values at engine init time in the engine itself, and by doing so minimise the amount of invariant platform and engine checks during each and every TLB invalidation. v2: * Fail engine probe if TLB invlidations registers are unknown. v3: * Rebase. v4: * Fix handling of GEN8_M2TCR. (Andrzej) v5: * Tidy checkpatch warnings. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Andrzej Hajda <[email protected]> Cc: Matt Roper <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> # v1 Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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