diff options
| author | John Crispin <[email protected]> | 2012-07-22 08:55:57 +0200 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2012-08-01 17:57:04 +0200 |
| commit | e29b72f5e129b4dd4b77dc01dba340006bb103f8 (patch) | |
| tree | f0425aa961e2becc0e4454eba8d04832be6eda74 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf | |
| parent | 2e3ee613480563a6d5c01b57d342e65cc58c06df (diff) | |
MIPS: Lantiq: Fix interface clock and PCI control register offset
The XRX200 based SoC have a different register offset for the interface
clock and PCI control registers. This patch detects the SoC and sets the
register offset at runtime. This make PCI work on the VR9 SoC.
Signed-off-by: John Crispin <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/4113/
Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf')
0 files changed, 0 insertions, 0 deletions