diff options
| author | Sudeep Holla <[email protected]> | 2015-01-21 12:02:30 +0000 |
|---|---|---|
| committer | Arnd Bergmann <[email protected]> | 2015-02-25 17:12:21 +0100 |
| commit | 7934d69abfa98392433c03136025b71972851733 (patch) | |
| tree | ce6d049d6a585d137d15c712189855f0fe68bc6c /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf | |
| parent | c517d838eb7d07bbe9507871fab3931deccff539 (diff) | |
arm64: Add L2 cache topology to ARM Ltd boards/models
Commit 5d425c18653731af6 ("arm64: kernel: add support for cpu cache
information") adds cacheinfo support for ARM64. Since there's no
architectural way of detecting the cpus that share particular cache,
device tree can be used and the core cacheinfo already supports the
same.
This patch adds the L2 cache topology on Juno board, FVP/RTSM and
foundation models.
Signed-off-by: Sudeep Holla <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Liviu Dudau <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf')
0 files changed, 0 insertions, 0 deletions