diff options
| author | Zhenyu Wang <[email protected]> | 2010-11-02 17:30:46 +0800 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2010-11-04 09:39:50 +0000 |
| commit | 16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c (patch) | |
| tree | 8a4d083794272b7d7bf82aad75076a7722164b23 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf | |
| parent | 8d0f56708292ca5c256ee3b7187d124afee81d93 (diff) | |
agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <[email protected]>
Cc: [email protected]
Signed-off-by: Chris Wilson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf')
0 files changed, 0 insertions, 0 deletions