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authorChen-Yu Tsai <[email protected]>2023-06-09 15:29:02 +0800
committerMatthias Brugger <[email protected]>2023-06-15 13:14:58 +0200
commit32dfbc03fc26a5aeeaff5b34d3d45f94be21cfae (patch)
treec2f54f971c7a21e0b7f2863859934c848b94b6e4 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace
parentc26f779a2295b81891078cc6f791856fa2705b50 (diff)
arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table
Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
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