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authorKuninori Morimoto <[email protected]>2015-01-15 08:09:26 +0000
committerMark Brown <[email protected]>2015-01-15 11:37:49 +0000
commit1ceeab2679069738fc73da6d8256014d3e195dab (patch)
tree325cc3c0b5d755a79cece7ae0a57388c135b88af /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace
parent765ae7c8dda7d06d7ce74b35beb4c7ec06b78643 (diff)
ASoC: rsnd: tidyup DMA start/stop timing on SSI
Current DMA starts after SSI, and stops before SSI. but we need to reverse these order. Otherwise, under/over run error might happen. Signed-off-by: Kuninori Morimoto <[email protected]> Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
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