irqchip: gic-v3: Initial support for GICv3

The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System register for the CPU interfaces (SRE)
- Support for more that 8 CPUs
- Locality-specific Peripheral Interrupts (LPIs)
- Interrupt Translation Services (ITS)

This patch adds preliminary support for GICv3 with ARE and SRE,
non-secure mode only. It relies on higher exception levels to grant ARE
and SRE access.

Support for LPI and ITS will be added at a later time.

Cc: Thomas Gleixner <[email protected]>
Cc: Jason Cooper <[email protected]>
Reviewed-by: Zi Shen Lim <[email protected]>
Reviewed-by: Christoffer Dall <[email protected]>
Reviewed-by: Tirumalesh Chalamarla <[email protected]>
Reviewed-by: Yun Wu <[email protected]>
Reviewed-by: Zhen Lei <[email protected]>
Tested-by: Tirumalesh Chalamarla<[email protected]>
Tested-by: Radha Mohan Chintakuntla <[email protected]>
Acked-by: Radha Mohan Chintakuntla <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Reviewed-by: Mark Rutland <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Jason Cooper <[email protected]>

0 files changed, 0 insertions, 0 deletions