diff options
| author | Lucas Stach <[email protected]> | 2022-07-06 15:28:11 +0200 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2022-08-11 01:45:32 +0200 |
| commit | ea6490b02240bd7939a3a13bc8d3f25046c01585 (patch) | |
| tree | 097c4c173edc7f36c446149cb7d74b0243a3d9cc /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | 5fa9e16191204b6ead0c31e8f3b6ef92ddd8183e (diff) | |
drm/bridge: tc358767: increase CLRSIPO count
The current CLRSIPO count is marginal and does not work with high
DSI clock rates. Increase it a bit to allow the DSI link to work at
up to 1Gbps lane speed.
Signed-off-by: Lucas Stach <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions