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| author | Mark Rutland <[email protected]> | 2014-08-01 10:23:20 +0100 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2014-08-01 14:00:06 +0100 |
| commit | ea1719672f59eeb85829073b567495c4f472ac9f (patch) | |
| tree | 32d444492c335db8d243243226822bb105ad446f /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | 94156675847c14a9b16e91b035da32e35e98ef79 (diff) | |
arm64: add newline to I-cache policy string
Due to a missing newline in the I-cache policy detection log output,
it's possible to get some ratehr unfortunate output at boot time:
CPU1: Booted secondary processor
Detected VIPT I-cache on CPU1CPU2: Booted secondary processor
Detected VIPT I-cache on CPU2CPU3: Booted secondary processor
Detected VIPT I-cache on CPU3CPU4: Booted secondary processor
Detected PIPT I-cache on CPU4CPU5: Booted secondary processor
Detected PIPT I-cache on CPU5Brought up 6 CPUs
SMP: Total of 6 processors activated.
This patch adds the missing newline to the format string, cleaning up
the output.
Fixes: 59ccc0d41b7a ("arm64: cachetype: report weakest cache policy")
Signed-off-by: Mark Rutland <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions