diff options
| author | Sheetal <[email protected]> | 2023-06-29 10:42:16 +0530 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2023-07-13 17:13:24 +0200 |
| commit | e483fe34adab3197558b7284044c1b26f5ede20e (patch) | |
| tree | 53ed6fb262d062da3c7fcdfa20c48130e8c496ac /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
arm64: tegra: Update AHUB clock parent and rate on Tegra234
I2S data sanity tests fail beyond a bit clock frequency of 6.144MHz.
This happens because the AHUB clock rate is too low and it shows
9.83MHz on boot.
The maximum rate of PLLA_OUT0 is 49.152MHz and is used to serve I/O
clocks. It is recommended that AHUB clock operates higher than this.
Thus fix this by using PLLP_OUT0 as parent clock for AHUB instead of
PLLA_OUT0 and fix the rate to 81.6MHz.
Fixes: dc94a94daa39 ("arm64: tegra: Add audio devices on Tegra234")
Cc: [email protected]
Signed-off-by: Sheetal <[email protected]>
Signed-off-by: Sameer Pujar <[email protected]>
Reviewed-by: Mohan Kumar D <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions