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| author | Geert Uytterhoeven <[email protected]> | 2016-09-21 16:31:41 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2016-10-17 15:56:21 +0200 |
| commit | c1b5371b72644907a9b81a7cd8eabb32f04466d1 (patch) | |
| tree | 7caa39c8f428e6da950f893afd4de625a5604062 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | 878f8baa02d4948637c1e0b41a6055b22eb1f4a5 (diff) | |
clk: renesas: cpg-mssr: Always use readl()/writel()
The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel()
and readl()/writel() to access the clock registers. Settle on the
generic readl()/writel().
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions