diff options
| author | Cruise Hung <[email protected]> | 2022-09-08 22:04:09 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-09-19 15:14:55 -0400 |
| commit | c1143ca2d523dee0f6012638068abd202a50a42b (patch) | |
| tree | 2aebd86073c4547d5498cce64a86394bd27af2a4 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | abffd871d4862f9e77979708d1df45152becf8b4 (diff) | |
drm/amd/display: Fix DP MST timeslot issue when fallback happened
[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.
[How]
Updated verified_link_cap with the new one from cur_link_settings
after the LT completes successfully.
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Wayne Lin <[email protected]>
Signed-off-by: Cruise Hung <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions