diff options
| author | Will Deacon <[email protected]> | 2011-10-07 15:57:55 +0100 |
|---|---|---|
| committer | Russell King <[email protected]> | 2011-10-08 10:05:34 +0100 |
| commit | a26bce1220a4c5a7a074a779e6aad3cae63a94f7 (patch) | |
| tree | b57a67eab4799e63e7fc699acd7682b8148ebbb8 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | c825dda905bac330c2da7fabdf5c0ac28758b3cd (diff) | |
ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores
ARMv6 cores do not implement the DBGOSLAR register, so we don't need to
try and clear it on boot. Furthermore, the VCR is zeroed out of reset,
so we don't need to zero it explicitly when a CPU comes online.
Tested-by: Marc Zyngier <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions