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| author | Tianyang Zhang <zhangtianyang@loongson.cn> | 2024-08-23 18:43:36 +0800 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-08-23 20:40:27 +0200 |
| commit | a1d4646d34c6642194a421ca9afbd060b0f9aa00 (patch) | |
| tree | 0c43161aacc1759f33e08c33769f3c1203865d44 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | 9e83dd3ebb14fadccb936308b7b101c75da76324 (diff) | |
irqchip/loongson-pch-msi: Prepare get_pch_msi_handle() for AVECINTC
On Loongson-3C6000 and higher systems with AVECINTC irqchip, there may
be multiple PCI segments, but only one PCH-MSI irq domain. In this case,
let get_pch_msi_handle() return the first domain handle.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Co-developed-by: Liupu Wang <wangliupu@loongson.cn>
Signed-off-by: Liupu Wang <wangliupu@loongson.cn>
Co-developed-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240823104337.25577-1-zhangtianyang@loongson.cn
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions