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authorPali Rohár <[email protected]>2021-10-28 20:56:57 +0200
committerLorenzo Pieralisi <[email protected]>2021-10-29 10:25:31 +0100
commit84e1b4045dc887b78bdc87d92927093dc3a465aa (patch)
treed0de14db4dbf976571021b4e84b81a58619f3b55 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py
parent771153fc884f566a89af2d30033b7f3bc6e24e84 (diff)
PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge
Aardvark controller has something like config space of a Root Port available at offset 0x0 of internal registers - these registers are used for implementation of the emulated bridge. The default value of Class Code of this bridge corresponds to a RAID Mass storage controller, though. (This is probably intended for when the controller is used as Endpoint.) Change the Class Code to correspond to a PCI Bridge. Add comment explaining this change. Link: https://lore.kernel.org/r/[email protected] Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
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