diff options
| author | Karthikeyan Ramasubramanian <[email protected]> | 2018-05-03 14:14:37 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2018-05-14 13:44:55 +0200 |
| commit | 7fb5b8800194c0d9a5d2aa8b3983cf7bc615b3ea (patch) | |
| tree | 6c72d1f2f6cdae7b3b326b316db06ba0001e51f9 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | f73717506151742ec580d52a6e427e333f853eef (diff) | |
tty: serial: qcom_geni_serial: Remove unnecessary memory barrier
While initiating TX, only the register reads need to be ordered. The
register write order either is achieved due to data dependency or is
not required.
Use readl to achieve the read order and remove the unnecessary barrier.
Signed-off-by: Karthikeyan Ramasubramanian <[email protected]>
Reviewed-by: Evan Green <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions