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authorTomasz Figa <[email protected]>2013-04-04 13:32:37 +0900
committerKukjin Kim <[email protected]>2013-04-04 15:51:08 +0900
commit74f7f8ba5092a76da1e9d07f245575cef86f15ab (patch)
treeee960840ee8829cedb53d6a083a5a836666c3398 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py
parent36fc09722d49077c6a602e8c07b06d21e798b75a (diff)
clk: exynos4: Use mout_mpll_user_* on Exynos4x12
Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
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