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authorStefan Riedmueller <s.riedmueller@phytec.de>2021-09-27 09:28:56 +0200
committerAbel Vesa <abel.vesa@nxp.com>2021-10-01 10:15:51 +0300
commit2f9d61869640f732599ec36b984c2b5c46067519 (patch)
tree4ea5c17c37885151026a5c3020bcaa6c9e7883e3 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py
parentd4e6c054fa953d06025b606b26939468df477fbf (diff)
clk: imx: imx6ul: Move csi_sel mux to correct base register
The csi_sel mux register is located in the CCM register base and not the CCM_ANALOG register base. So move it to the correct position in code. Otherwise changing the parent of the csi clock can lead to a complete system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely modified. Also remove the SET_RATE_PARENT flag since one possible supply for the csi_sel mux is the system PLL which we don't want to modify. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210927072857.3940880-1-s.riedmueller@phytec.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
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