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| author | Andre Przywara <[email protected]> | 2016-06-28 18:07:28 +0100 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2016-07-01 11:26:20 +0100 |
| commit | 290622efc76ece22ef76a30bf117755891ab27f6 (patch) | |
| tree | 565b544e4d178c78ab32d1246f5585ec922074c9 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | b82bfa4793cd0f8fde49b85e0ad66906682e7447 (diff) | |
arm64: fix "dc cvau" cache operation on errata-affected core
The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac" as well.
Attribute the usage of the instruction in __flush_cache_user_range
to also be covered by our alternative patching efforts.
For that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.
Signed-off-by: Andre Przywara <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions