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| author | Kenneth Graunke <[email protected]> | 2014-01-27 14:20:16 -0800 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2014-08-07 14:04:07 +0200 |
| commit | 02c9f7e3cfe76a7f54ef03438c36aade86cc1c8b (patch) | |
| tree | f06021f73f72939b07e978c843e77a8167b5fbb4 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | |
| parent | 884ceacee308f0e4616d0c933518af2639f7b1d8 (diff) | |
drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
must be preceded by a PIPE_CONTROL with the "CS Stall" bit set.
Documented on the BSpec 3D workarounds page.
Reviewed-by: Rafael Barbalho <[email protected]>
Signed-off-by: Kenneth Graunke <[email protected]>
[vsyrjala: add chv w/a note too]
Signed-off-by: Ville Syrjälä <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py')
0 files changed, 0 insertions, 0 deletions