diff options
| author | Zhuoyu Zhang <[email protected]> | 2014-03-18 13:41:25 +0800 |
|---|---|---|
| committer | Rafael J. Wysocki <[email protected]> | 2014-03-20 03:37:17 +0100 |
| commit | bfa709bc823fc32ee8dd5220d1711b46078235d8 (patch) | |
| tree | 04ef279dd3a82117c9282d77101744dbe3cafbe6 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py | |
| parent | 0b443ead714f0cba797a7f2476dd756f22b5421e (diff) | |
cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SoCs
According to the data provided by HW Team, at least 12 internal platform
clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs.
This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition
latency to make DFS governors work normally on Freescale e500mc boards.
Signed-off-by: Zhuoyu Zhang <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py')
0 files changed, 0 insertions, 0 deletions